FIG. 1 illustrates a multiprocessing system 100 having a central processor ("CP") chips 101, which may also include secondary (L2) caches, coupled to memory controllers 102. Memory controllers 102 may be coupled to memory card controllers 105 directly or through a transceiver 103. Each of the memory card controllers 105 may be part of a memory card 104, including a plurality of DRAMs 106. A plurality of buses couple components 101-106 to each other in various configurations.
Efforts are continuously made to increase the speed by which these components 101-106 process data. However, one of the limiting factors regarding the maximum speed by which the entire system 100 can operate is the speed that data can be transferred over these buses between the components. A typical bus operation has been the transfer of a data bit on each bus line between two components one at a time. In other words, the next data bit is not transferred until the previous data bit has been successfully latched by the receiving component. In order to increase this transfer speed, multiple bits may be transferred in succession over each bus line without this requirement that a subsequent bit wait until a previous bit has been successfully received. In other words, a snapshot of a bus line would show that there are a plurality of bits presently traveling between the components on any one bus line.
To transfer multiple bits over each bus will increase data transfer frequency significantly or reduce the data transfer cycle time significantly. To properly capture the signal of a multiple lines data bus, the data arrival time at the receiver of all the lines has to fall into a timing window. The length of such a timing window is related to the length of data transfer cycle. As the cycle time is reduced, the capture timing window is also reduced.
Since a bus has a plurality of bus lines for sending a plurality of bits in parallel (which are often associated with a particular word), if certain factors operate to cause one or more of these bits to travel faster or slower than the other bits traveling in parallel, there is the possibility that the receiving component will only receive a portion of a data word before the next data word arrives. With the prior art method of data transfer, the cycle time is relatively high, and thus the miscapturing of data from different cycles will not occur.
Such delays may be caused by one or more of several reasons, including the non-uniform length of the various bus lines within a bus. Referring to FIG. 2, there is illustrated components 201 and 202 interconnected by a bus having bus lines 203-210. As can be seen, lengths of bus lines 203-210 vary depending upon their layout on the printed circuit board. It can be readily appreciated that at high speeds, the time it takes for a bit to travel over bus line 205 will be greater than the time for a parallel bit to travel over bus line 206. Another factor may be the different positioning of the various drivers within one of the components for driving the bits onto the bus lines. These driver circuits may be in different locations on the chip, and furthermore, the fabrication processes utilized to manufacture the chip may result in different operating speeds for these various drivers. Uneven processing may also account for variations in the quality of the individual bus lines. Further, the power supply noise will vary the delay of a driver. The power supply noise can also vary the timing of the launching clock which in turn can change the data bus signal timing.
As a result of such factors, skew may be introduced into one or more of the bus lines resulting in an unsatisfactory delay in the arrival of bits over these bus lines. Such unsatisfactory delays hamper the ability of the capture latch to capture the signal for multiple data words to be transferred at one time over the bus.
Some of these factors which affect the timing of the signal are invariant with respect to time such as the length difference between signal lines. Some of these factors are variant with time such as the driver delay variation due to power supply. A static compensation technique can be used to compensate the time invariant skews.
As a result, there is a need in the art for a technique for compensating for such skew.